A semiconductor memory device is composed of a large number of memory cells. When one of these memory cells does not operate normally, the memory device cannot perform its proper function. Moreover, as the integration density of semiconductor memory devices increases, the probability of abnormal operation of memory cells also increases. Accordingly, semiconductor memory devices are tested to sort out defective cells. A bit-by-bit test method and a parallel bit test method have been proposed for testing semiconductor memory devices.
Meanwhile, to improve the performance and increase the speed of semiconductor memory devices, Rambus Dynamic Random Access Memories (DRAMs) have been developed. A Rambus DRAM reads from an entire memory cell array at once, storing a large amount of data and outputting the data at high speed in synchronization with a clock signal. This data transmission is implemented using a pipeline. FIG. 1 is a diagram illustrating a pipeline in a semiconductor memory, according to the prior art.
In the pipeline of FIG. 1, a plurality of unit pipeline cells (UPLs) 110 through 117 (hereinafter collectively referred to as "UPLs 110-117") are connected in series. Each of the plurality of UPLs 110-117 transmits stored data to the succeeding UPL stage and latches data from the preceding UPL stage in response to control signals WRTPIPE, WRTPIPE_B, LOAD and LOAD_B and clock signals TPCLK and TPCLK_B. The signals WRTPIPE_B, LOAD_B and TPCLK_B are the inverted signals of the signals WRTPIPE, LOAD and TPCLK, respectively. In this pipeline, data RD&lt;0&gt; through RD&lt;7&gt; (hereinafter collectively referred to as "RD&lt;0&gt;-RD&lt;7&gt;") of predetermined data bits are sequentially transmitted to a pad DQ0 via the UPL stages.
FIG. 2 is a timing diagram of some of the signals corresponding the operation of the pipeline of FIG. 1. Similar to the operation of a typical DRAM, data is read from memory cells corresponding to activated row and column addresses RADR and CADR, respectively, and applied to a data line RD&lt;7:0&gt;. During a pipeline data read operation in response to a binary logic "low" pipeline write signal WRTPIPE and a preceding stage data latch signal LOAD, read memory cell data RD&lt;0&gt;-RD&lt;7&gt; are sequentially output in synchronization with the clock signal TPCLK.
However, in the pipeline, output data cannot be tested for defective values until all the data is output in response to the clock signal TPCLK. In other words, the test is performed in bit units. Accordingly, eight edges of the clock signal TPCLK are required for testing the eight data RD&lt;0&gt;-RD&lt;7&gt;. Rambus DRAMs having a pipeline are composed of a plurality of data lines, so a large number of cycles of the clock signal TPCLK are required for testing one Rambus DRAM. Consequently, the time required to perform a test is undesirably long. Since several million Rambus DRAMs are produced per month, a large amount of time is required to test the same. A long test time increases the cost associated with manufacturing the Rambus DRAMs, as well as decreasing productivity.
Accordingly, it would be desirable and highly advantageous to have a semiconductor memory device capable of reducing the test time of a pipeline therein.